It is known that serial digital data communication receivers must be synchronized to the incoming serial data rate in order to properly recover the data. A circuit called a phase locked loop has been employed for this purpose. A phase locked loop is responsive to the data rate of the incoming serial data, and compares the timing of said incoming data to a clock pulse being generated by a voltage controlled oscillator (VCO) in the receiver. Whenever any difference in frequency or phase between these two signals is sensed, a phase error signal is generated which is used to resynchronize the VCO. Extreme stability, accuracy and speed of response to correct the VCO has become more important for the higher communications data rate of the fiber and microwave links. Several of these different types of communication links employ different data rates such as ESCON at 200 MHz and Fibre Channel Specification (ANSI X3T9.3) at 266.7 MHz. The portion of the phase locked loop which compares the incoming serial data to the VCO is called a phase detector. Prior art phase detectors could not be optimally operated over the wide frequency ranges of these applications and therefore required a different design for each application. The range of the prior art phase detectors was sensitive to frequency and pulse width so that they could not reliably operate at both the high and low frequencies in the frequency range of interest. Also, the acquisition frequency, i.e., the frequency over which lock could be reacquired if it were lost during operation, was limited.
It is the object of our invention to provide a novel phase shifter and a phase detection method and a phase detector having a constant gain region which is a fixed percentage of the period over the operative frequency range.